The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to trench sidewall protection for selective epitaxial semiconductor material formation.
In the manufacture of integrated circuit devices such as field effect transistors (FETs) it is sometimes desirable to selectively add semiconductor material to an existing, preformed semiconductor structure prior continuing with subsequent processing steps. For example, in planar transistor configurations, a raised source/drain region is a semiconductor region that is formed on a pre-existing semiconductor region of an FET and functions as a part of the source/drain region of the field effect transistor. A raised source/drain region can be formed on a pre-existing source/drain region by a selective deposition process, which selectively deposits additional semiconductor material on exposed semiconductor surfaces without depositing any semiconductor material on dielectric surfaces.
In another example, non-planar FETs incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor structure is known as the finFET, which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width. Due to the advantageous feature of full depletion in a finFET, the increased number of sides on which the gate electrode controls the channel of the finFET enhances the controllability of the channel in a finFET compared to a planar MOSFET. The improved control of the channel allows smaller device dimensions with less short channel effects as well as larger electrical current that can be switched at high speeds. A finFET device generally has faster switching times, equivalent or higher current density, and much improved short channel control than planar CMOS technology utilizing similar critical dimensions.
In certain instances, it is desirable to selectively merge selected regions of predefined fin structures, such as through selective epitaxial growth of a semiconductor material.
Regardless of whether a device is a planar transistor or a finFET, it is desirable to be able to precisely control where such additional regions of semiconductor materials are formed.